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Processor concurrent PCI read

开发者 https://www.devze.com 2023-04-04 05:37 出处:网络
I\'开发者_JAVA百科m working on a project which uses a LEON2 (SparcV8) processor and we have a PCI bus that connects other FPGA and the processor.

I'开发者_JAVA百科m working on a project which uses a LEON2 (SparcV8) processor and we have a PCI bus that connects other FPGA and the processor.

Running on this we have a multitasking application using RTEMS and written in C.

Now I'm not familiar at all with processor and pci architecture that's why I come to you guys for enlightenment.

The problem is this : Consider that we have one RTEMS task that performs a read of memory on the PCI bus. On our board a PCI access is approximatively 2us long. Now a colleague of mine raised an issue, what if during that PCI read the task scheduler of RTEMS decided that it was time for another task to fire, and that this task job is to also perform a PCI read. His point is that the first PCI read performed before the task switching would be corrupted by the second PCI read which would be performed by the second task before the first one is performed.

Could this case happen ?

My point of view is that this problem shouldn't happen because for me, a PCI read is like any other memory read, only that instead of reading the local RAM which is for example at address 0x4000'0000, we read address 0xA020'0000 the processor then converts this as being an address on the PCI bus and perform this read thru the bus. Sure this read is longer than a local memory read but this process should not be interruptible in the middle. My understanding may very well be completely off, in that case feel free to correct me !


Note: I am referring to PCI Express (PCIe). PCI might be a little different - I am not familiar with it.

That depends on the PCIe core (module) that performs the read.

Basically to perform a Memory Read, the PCIe core sends a MemRd packet on the bus that is tagged. The data itself arrives in a Completion packet with the same tag. So the read is not "corrupted".

Now, the PCIe core might block the CPU until the Completion packet is received, or it can release the CPU right after the MemRd packet is sent. In such a case the PCIe core will need to be able to handle several concurrent pending reads.

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