vhdl

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How can I write a simple pseudo assembler?

I have to write a series of testbenches for a simple cpu model written in VHDL. What I need is a piece of code that translates an instruction in assembly code (MIP开发者_开发百科S) into a binary strin[详细]

2023-01-28 03:41 分类：问答
Can SystemC diplay circuits as a drawing?

I need to design some digital circuits , but it kills me drawing them by hand. I\'ve searched a easier way to do them, and found VHDL and what\'s more interesting SystemC. The last one is pretty nice[详细]

2023-01-26 02:12 分类：问答
Universal shift arithmetic right in VHDL

I am designing universal shift arithmetic operator. Is there a better way to achieve it besides using the 32bit multiplexer (decoder) in a way presented bellow?[详细]

2023-01-25 12:50 分类：问答
Preserving the widths of ports

I am trying to re-use netlists in other designs without the success. I have a component which is translated to the netlist:[详细]

2023-01-25 07:06 分类：问答
Reading OUT ports for debugging

I have a FIFO which has an interface that looks something like this: entity fifo is port ( CLK: INstd_logic := \'0\';[详细]

2023-01-23 21:45 分类：问答
Problem with net instantiation

I have a very simple statemachine that sets some control signals to interact with a third party IP. The code looks roughly as follows:[详细]

2023-01-23 04:39 分类：问答
Error adding std_logic_vectors

I w开发者_运维技巧anna have a simple module that adds two std_logic_vectors. However, when using the code[详细]

2023-01-22 14:30 分类：问答
"Serialize" VHDL record

Suppose I have the following type definition which relies on constants to indicate vector length of the record members:[详细]

2023-01-21 12:08 分类：问答
Reset an Altera M9K's content to 0 (power-up value)

Good day, I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well.[详细]

2023-01-21 11:29 分类：问答
Making a 4-bit ALU from several 1-bit ALUs

I\'m trying to combine several 1 bit ALUs into a 4 bit ALU. I am confused about how to actually do this in VHDL. Here is the code for the 1bit ALU that I am using:[详细]

2023-01-21 06:40 分类：问答