hdl

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minimization of program segment - if, else

X, Y, Z, T are different jobs. Ex, X = Multiplexer( ... )开发者_JAVA技巧 if ( empty1 ) if ( empty2 )[详细]

2023-02-24 00:10 分类：问答
Purpose to providing more than one architecture?

I\'m in the process of learning VHDL and I\'m trying just learning from examples, syntax guides, and experiments.[详细]

2023-02-21 20:45 分类：问答
Driving bidirectional lines in Verilog

this question probably wont be explained very well and that\'s because I don\'t really understand what\'s happening in my design.[详细]

2023-02-12 20:48 分类：问答
Simulation vs hardware mismatch

I have a very simple problem but I do not get my head around what is going wrong. Essentially, the whole thing works fine when simulating it, however, having it[详细]

2023-02-10 22:17 分类：问答
What are the requirements to meet in order to ISE auto infer ram blocks?

I have this piece of IP that is supposed to be a 32 bits byte addressable memory. But I can\'t make it infer block rams, it is inferring a huge amount of flip flops...[详细]

2023-02-10 12:18 分类：问答
Reading an image to FPGA from PC and Back

I need to read a small image (tif format) from PC to FPGA kit (ALTERA DE2-70) for processi开发者_StackOverflow社区ng, then write it back to PC. I have no idea how to do it in Verilog?[详细]

2023-01-31 09:54 分类：问答
Universal shift arithmetic right in VHDL

I am designing universal shift arithmetic operator. Is there a better way to achieve it besides using the 32bit multiplexer (decoder) in a way presented bellow?[详细]

2023-01-25 12:50 分类：问答
Preserving the widths of ports

I am trying to re-use netlists in other designs without the success. I have a component which is translated to the netlist:[详细]

2023-01-25 07:06 分类：问答
In Specman, why is my macro label for the code body returning garbage?

Similar to this post http://feedproxy.google.com/~r/cadence/community/blogs/fv/~3/IvdCIla8_Es/extending-multiple-when-subtypes-simultaneously.aspx[详细]

2023-01-17 18:12 分类：问答
Can Verilog testbenches work with a real clock?

I wrote a counter in Verilog, and then a testbench to test it. My testbench gives the correct results, so my code is OK. But is it gives the result of a long time instantly.[详细]

2023-01-05 09:02 分类：问答