How to force make to run clean target if makefile changed

If makefile changes, make rebuilds all targets right?

But how to tell make that if after makefile changed, i开发者_开发技巧t shall run make clean and then make?

Or how to instruct make to run some other command in that situation? Do I have to write a special kind of target?

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You could try this:

all: Makefile.uptodate yourMainTarget

Makefile.uptodate: Makefile
    make clean
    touch Makefile.uptodate

I'm not a make expert so I don't know if that's a horrible hack, but it worked in my limited tests ;-)

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Crude but effective (I can't think of anything more elegant):

include marker

marker: Makefile
    @touch $@
    $(MAKE) clean
    $(MAKE)

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I believe that you want to run clean automatically because you want certain targets to be rebuilt whenever make is called. This can be achieved by adding a dependency named FORCE to the rule whose target you want to build always and then define FORCE like this: ie no rule and no dependency.

FORCE:

Please see http://www.gnu.org/software/make/manual/make.html#Force-Targets

If you want all files to be recompiled, you add the following to the makefile:

%.o : %.cpp FORCE
    $(CXX) -c $(CXXFLAGS) $< -o $@