Make Implicit Dependancy

In a Makefile, is there any way of making a rule an implic开发者_开发问答it dependency of all other rules?

Say, for instance, i wanted a rule run whenever the Makefile is run, regardless of which rule is actually being requested. How would i do that?

---

I have no idea why you'd want to do this, but in GNU make you can do this by -include-ing a .PHONY file:

.PHONY: run-always
-include run-always
run-always:
    echo "trololol"

---

Include a wildcard rule:

%: mydependency

I've tried this, the following makefile is a proof of concept

all: a b

a:
    touch $@

%: ccc
    #

ccc::
    touch ccc

Note the use of

1. Double-Colon Rule
2. Match-Anything Pattern Rule

In order to prevent the dependency from building unconditionally each time, you might want to make it an indirect dependency (requirement for the ccc:: rule above, instead of directly on the wildcard rule).

Good luck