verilog

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USRP2 FPGA debugging

I have added some functionalityin the FPGA code( Verilog) in USRP2. I would like to debug the code. Can you please suggest开发者_JS百科, how to debug the FPGA code .[详细]

2023-04-01 15:16 分类：问答
Is the 2D array synthesizable in verilog

The memory is always 1D so does the 2D or 3D array which works fine in simulation gets synthesized in verilo开发者_开发技巧g?(the word size is 8 bit)It depends on the synthesis tool and what you are t[详细]

2023-03-29 13:36 分类：问答
how to test simulation results for 256 point FFT written in verilog code

I have written verilog code for 256 point FFT(radix22 sdf) and testbench (which has random sample values...)[详细]

2023-03-29 12:04 分类：问答
Why can't I instantiate inside the procedural block in Verilog

I need to instantiate some modules whose requirements pop u开发者_运维百科p during the procedural block.But I am not allowed to instantiate inside the procedural block.Where else should I instantiate[详细]

2023-03-29 09:32 分类：问答
Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

I have been trying to fin开发者_Python百科d the Absolute value of an integer which is designated to Verilog core using Xilinx SystemC, what I have seen is that Verilog treats the negative number as a[详细]

2023-03-27 01:47 分类：问答
Synthesis error in Verilog

I am trying to implement the FatICA algorithm in verilog. I have written the whole code and till simulation it shows no error but when I try to synthesize the code it gives an error stating \" \";\" e[详细]

2023-03-25 15:48 分类：问答
How to know if HW/SW codesign will be useful for a specific application?

I will be in my final year (Electrical and Computer Engineering )the next semester and I am searching for a graduation project in embedded systems or hardware design . My professor advised me to searc[详细]

2023-03-24 07:50 分类：问答
Changing user_logic.v for my program

I just made a custom IP in Xilinx it generated a user_logic file which i required in Verilog, but i am having problems changing the code.[详细]

2023-03-18 09:21 分类：问答
Parameterized Bit-fields in verilog

Is it possible to parameterize a bit-field in verilog? Essentially I want to use a parameter or alternative to define a bit-range. The only way I can think of doing this is with a 开发者_运维技巧`defi[详细]

2023-03-15 04:59 分类：问答
Simple Verilog VPI module to open audio files

I would like to write a VPI/PLI interface which will open audio files (i.e. wav, aiff, etc) and present the data to Verilog simulator. I am using Icarus at the moment and wish to[详细]

2023-03-13 21:28 分类：问答