verilog_开发者

Why is System Verilog $display not executing when I expect it to?

In my bench program, I have something like this (simplified): // bench.sv program tb (input clk, ...); initial begin[详细]

2023-04-12 15:43 分类：问答

Is there any special significance of a parenthesis in Verilog when used to wrap a parameter?

I have a piece of Verilog code worked upon by a programmer no longer in the company I work for. An extract is given below:[详细]

2023-04-12 11:44 分类：问答

bit vector range selection with runtime value in system verilog

Let\'s say I have a vector value[6:0] and an input vector input[3:0]. The problem is I want to set a number of bit in value vector to 1 base on value of input, e.g.:[详细]

2023-04-12 03:18 分类：问答

How can I output a value to a register with a Verilog task?

My understanding of Verilog tasks is that they act like subroutines and are able to accept both input and output parameters. Using $display, I can peek at the values of my register variables along the[详细]

2023-04-09 06:02 分类：问答

how can i know if my code is Synthesizable? [Verilog]

In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structu开发者_如何转开发ral circuit[详细]

2023-04-07 15:37 分类：问答

Verilog Barrel Shifter

I want to create a 64-bit barrel shifter in verilog (rotate right for now). I want to know if there is a way to do it without writing a 65 part case statement? Is there a way to write some simple code[详细]

2023-04-07 01:36 分类：问答

Why is my mux not producing an output in Verilog?

I\'ve written what I thought would be a working MUX, but my output is stubbornly staying at high-impedance. Can someone please provide me with guidance?[详细]

2023-04-06 19:22 分类：问答

Converting a wire value in Verilog for further processing

I\'m new to Verilog. I have written code to conve开发者_JS百科rt a wire value to an integer: wire [31:0] w1;[详细]

2023-04-06 10:38 分类：问答

Accessing Verilog genvar generated instances in simulation code

This is a Verilog releated question. I am working with XILINX ISE as a dev environment. I am trying to access variables in the simulation that are automatically generated using genvar but I am receiv[详细]

2023-04-03 03:08 分类：问答