xilinx

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How to determine how many slices a design uses

I\'ve implemented a 16-bit ALU and a register file in VHDL using the Xilinx ISE.I\'ve been asked how many slices my design uses, and I have no idea how to go about answering that question.I\'m not wor[详细]

2023-04-11 20:28 分类：问答
Xilinx Error: Place 1018 message

I am using a Basys2 board to program a simple string detector to read patterns like \"0101\". I am using the Xilinix Design Suite 13.2 for this project. The.ucf file gives the following message.[详细]

2023-04-08 05:38 分类：问答
How to initiate BRAMs with image data

I would like to initiate some BRAMs (I\'m using Xilinx FPGAs and ISE) with data from an image. It\'s bound to be thr开发者_StackOverflow中文版ough coe files but how? I could write a Java applet to man[详细]

2023-04-03 06:04 分类：问答
Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

I have been trying to fin开发者_Python百科d the Absolute value of an integer which is designated to Verilog core using Xilinx SystemC, what I have seen is that Verilog treats the negative number as a[详细]

2023-03-27 01:47 分类：问答
Book suggestions for Low-level ethernet/networking (e.g. MII) [closed]

Closed. This question is seeking recommendations for books, tools, software libraries, and more. It does not meet Stack Overflow guidelines. It is not currently accepting answers.开发者_JAVA百科[详细]

2023-03-24 21:55 分类：问答
Xilinx ISE fails to use std_logic_1164

I have Xilinx ISE 13.1 installed on an ACER laptop with Win7 (64bit). After installing the software (WebPACK version) I created an empty VHDL module and ran \"check syntax\". The process failed with[详细]

2023-03-23 08:57 分类：问答
Running time vary on Microblaze after code modification

When I do开发者_JAVA百科 some modifications in my code that runs on Microblaze, I sometimes see a large discrepancy in runtime for the execution of code that follows the same path. To illustrate, what[详细]

2023-03-22 03:37 分类：问答
Changing user_logic.v for my program

I just made a custom IP in Xilinx it generated a user_logic file which i required in Verilog, but i am having problems changing the code.[详细]

2023-03-18 09:21 分类：问答
Error during Netlist Generation in Simulink

I was trying to generate a netlist from a simple Model in simulink. I can run the simulation开发者_运维百科 (usingsysgen).[详细]

2023-03-16 15:32 分类：问答
Problem with Parallel-to-Serial block in Simulink

I am trying to convert the input word coming out of the DQPSK Demodulator (Type : UFix2_0) to a serial stream.[详细]

2023-03-14 00:54 分类：问答